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June 1997
NDP6030PL / NDB6030PL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as DC/DC converters and high efficiency
switching circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
Features
-30 A, -30 V. R DS(ON) = 0.042 ? @ V GS = -4.5 V
R DS(ON) = 0.025 ? @ V GS = -10 V .
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R DS(ON) .
175°C maximum junction temperature rating.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings
T C = 25°C unless otherwise noted
Symbol
V DSS
V GSS
Parameter
Drain-Source Voltage
Gate-Source Voltage - Continuous
NDP6030PL
-30
±16
NDB6030PL
Units
V
V
I D
Drain Current
- Continuous
-30
A
- Pulsed
-90
P D
T J ,T STG
T L
Total Power Dissipation @ T C = 25 ° C
Derate above 25 ° C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
75
0.5
-65 to 175
275
W
°C
°C
1/8" from case for 5 seconds
T J ,T STG
Operating and Storage Temperature Range
-65 to 175
°C
THERMAL CHARACTERISTICS
R θ JC
R θ JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
2
62.5
° C/W
° C/W
? 1997 Fairchild Semiconductor Corporation
NDP6030PL Rev.B1
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